1. Field of the Invention
The present invention relates, in general, to a ball grid array (BGA) package substrate and a method of fabricating the same and, more particularly, to a BGA package substrate, in which a wire bonding pad and a solder ball pad are formed on a via hole, making high freedom in design of a circuit pattern and a high density circuit pattern possible, and a method of fabricating the same.
2. Description of the Prior Art
Recently, technologies with respect to a BGA package substrate have rapidly been developed so as to realize light, compact and high density microcircuit patterns in accordance with the trend toward miniaturization, high integration, and multi-functionalization of electronic goods. Particularly, the light and compact microcircuit patterns are frequently needed in CSP (chip-sized package) goods in which a semiconductor device is mounted on the BGA package substrate.
Furthermore, it is required that mobile phones, to which the CSP goods are most frequently applied, have multiple functions, in other words, it is required to continuously add novel functions to existing functions of the mobile phones. Thus, the number of signal lines of the semiconductor device is rapidly growing. With respect to this, in order to mount the semiconductor device having a large number of signal lines, it is required to increase freedom in design of the BGA package substrate.
FIGS. 1a to 1g are sectional views illustrating the fabrication of a conventional BGA package substrate, FIG. 2 is a sectional view of a conventional BGA package substrate on which a semiconductor device is mounted, and FIG. 3 illustrates a conventional inferior BGA package substrate.
As shown in FIG. 1a, after a copper clad laminate 11, in which copper foil layers 13, 13′ are formed on both sides of an insulating resin layer 12, is prepared, internal layer circuit patterns are formed on the copper foil layers 13, 13′ of the copper clad laminate 11. Subsequently, prepregs 14, 14′ and copper foils 15, 15′ are layered on both sides of the copper clad laminate 11 on which the internal layer circuit patterns have already been formed.
As shown in FIG. 1b, blind via holes (a), which connect the copper foil layers 13, 13′ to the copper foils 15, 15′ therethrough, are formed using a laser to achieve circuit connections between the copper foil layers 13, 13′ and the copper foils 15, 15′, and a through hole (b) is formed using a mechanical drill to connect the upper and lower copper foils 15, 15′ to each other therethrough.
As shown in FIG. 1c, copper plating layers 16, 16′ are formed on the upper and lower copper foils 15, 15′, walls of the blind via holes (a), and a wall of the through hole (b) to electrically connect the blind via holes (a) to the through hole (b).
As shown in FIG. 1d, external layer circuit patterns are formed on the upper and lower copper foils 15, 15′ and the copper plating layers 16, 16′ using a photolithography process.
As shown in FIG. 1e, solder resists 17, 17′ are applied on upper and lower sides of the resulting substrate, on which the external layer circuit patterns are formed, and then subjected to a pseudo-drying process.
As shown in FIG. 1f, openings (c) are formed through the upper solder resist 17 using a photolithography process so as to correspond to wire bonding pads, and openings (d) are formed through the lower solder resist 17′ so as to correspond to solder ball pads.
As shown in FIG. 1g, gold plating layers 18 are formed on the wire bonding pads that correspond in position to the openings (c) of the upper solder resist 17, and gold plating layers 18′ are formed on the wire bonding pads that correspond in position to the openings (d) of the lower solder resist 17′, thereby creating the conventional BGA package substrate 10.
As shown in FIG. 2, a semiconductor device 20 is attached to the conventional BGA package substrate 10 using an adhesive 30, wire bonds 40 are formed between the wire bonding pads and the semiconductor device 20, and solder balls 50 are formed on the solder ball pads.
The fabrication of the conventional BGA package substrate 10 as described above is disclosed in Korean Patent Registration Nos. 190,622, 328,251, and 340,430.
In the conventional BGA package substrate 10, surfaces of the wire bonding pads must be even in order to form the wire bonds 40 that are connected between the semiconductor device and the wire bonding pads to connect the semiconductor to signal lines. Therefore, the wire bonding pads and the blind via holes for transmitting signals, which flow through the wire bonding pads, to circuit layers therethrough must be formed at different positions.
If the wire bonding pads are formed on the blind via holes, since exposed portions of the blind via holes are uneven in the conventional BGA package substrate 10, it is difficult to form the wire bonds 40 due to uneven surfaces of the wire bonding pads.
Therefore, the wire bonding pads and the blind via holes must be formed at different positions in the conventional BGA package substrate 10, thus large areas are wasted on the external layer circuit patterns of BGA package substrates 10 as they tend to have high density.
Additionally, in the conventional BGA package substrate 10, the solder ball pads and the blind via holes for transmitting signals, which flow through the solder ball pads, to circuit layers therethrough must be formed at different positions so as to form the solder balls 50 that are to be connected to a mother board.
If the solder ball pads are formed on the blind via holes, since it is difficult to completely remove the solder resist 17′ from walls and bottoms of the blind via holes in the conventional BGA package substrate 10, adhesion strength between the exposed solder resist 17′ and the solder balls 50 is poor, and thus, undesirably, the solder balls 50 are easily separated from the solder resist 17′.
Accordingly, the solder ball pads and the blind via holes must be formed at different positions in the conventional BGA package substrate 10, thus large areas are wasted on the external layer circuit patterns of BGA package substrates 10 as they tend to have high density.
To avoid the above disadvantages, a plan, in which a fill plating process is conducted to fill the blind via holes (a) in the course of forming the copper plating layers 16, 16′ in FIG. 1c, is suggested.
However, the fill plating process is problematic in that since the blind via holes (a) are filled with costly chemicals, the fabrication cost of the BGA package substrate 10 increases.
In addition, the fill plating process is problematic in that voids or dimples are easily formed when sizes of the blind via holes (a) are reduced.
Furthermore, as shown in FIG. 3, the conventional BGA package substrate 10 is problematic in that voids (e) are formed in portions of the solder resists 17, 17′ corresponding in position to the blind via holes (a) because the solder resists 17, 17′ having high viscosity do not completely fill the blind via holes (a) when high density microcircuit patterns are required. Internal pressure of the BGA package substrate 10 increases with an increase in a temperature of the substrate during operation of the semiconductor device 20, thus the voids (e) act as a cause for the occurrence of burst of the voids (e), cracks, and interruptions in circuit patterns.